Heretofore, as a counting apparatus which carries out a counting operation while monitoring for whether or not the counting operation is being carried out normally, there is for example a device as disclosed in Japanese Examined Patent Publication No. 4-41532, which is utilized in a time element circuit.
In this time element circuit, there is provided two oscillators having different oscillation frequencies, the arrangement being such that when an input voltage is lost, a high frequency oscillation output from one of the oscillators is input to a counter. When the high frequency oscillation output reaches a predetermined number the counter is set, and due to the output from the counter, a delay output from after the loss of the input voltage is self held. Then due to the self held output, a low frequency oscillation output from the other oscillator is input to the counter. Subsequently, when the low frequency oscillation output attains a predetermined number, the counter is reset and the output from the self hold circuit is stopped. More specifically, the construction is such that the number of inputs of low frequency oscillation outputs is counted from after the high frequency oscillation output has reached a predetermined number, to thereby obtain the delay time. By using a counting apparatus in this way, the precision of the time element circuit is increased.
However, with the above described conventional counting apparatus applied to a time element circuit, monitoring for whether or not the counter is operating normally is carried out before counting the low frequency oscillation output, at the point in time of starting the counting operation for the low frequency oscillation output. This is done by making the counter carry out a high speed counting operation using the high frequency oscillation output. That is to say, with the conventional counting apparatus, the construction is such that monitoring of the operation of the counter is carried out before the counting operation for the input signal of the signal being counted.
In practice however, whether or not the counter is operating normally, should be ascertained after completion of the counting operation for the input signal of the signal being counted, so that the latest operating condition for the counter is monitored.
Moreover, the above described counter is generally an electronic circuit comprising a plurality of frequency dividers connected in cascade. For this to be a so called fail-safe counter where an input pulse signal of the signal being counted is counted and an output is not produced until this reaches a predetermined number, while at the time of a fault, the generation of an output is never premature, then for the counter to fulfill the important role in a control where safety is of concern, the abovementioned fail-safe counter performance is required.
Conventional counters however do not necessarily satisfy the abovementioned fail-safe counter performance.
For example, a counter may be considered wherein n frequency dividing circuits made up of flip-flop circuits (referred to hereunder as F.cndot.F circuits) are connected in cascade. Here if the signal being counted is a clock signal, then the counting operation is carried out using, for example, the falling of the clock signal.
In this case the frequency dividing circuits are reset when a reset signal of an L level is input to an active low reset terminal, and the counting operation is started when the reset signal rises to an H level. Then, after the reset signal rises, and once 2.sup.n-1 clock signals have been input, the n-1th frequency dividing circuit output drops and the output from the final frequency dividing circuit rises, and a count output is produced indicating that the number of inputs of clock signals has reached a predetermined number.
However, in the case for example where the reset terminal of the n-1th frequency dividing circuit has an open fault, then even if the reset signal is input, the n-1th frequency dividing circuit cannot be reset. In this case, when the reset is released and the counting operation started, it is not possible to know if the n-1th frequency dividing circuit is in the reset condition. If the n-1th frequency dividing circuit is in the reset condition (the output is an H level), then after commencement of the counting operation, the output from the n-1th frequency dividing circuit falls at the point in time when the 2.sup.n-2 clock signals are input, and at this point in time, the output from the final stage frequency dividing circuit rises and the counter output is thus produced.
That is to say, after commencement of the counting operation, the counter output which should rise at the point in time of input of the 2.sup.n-1 clock signals, rises at the point in time of input of the earlier 2.sup.n-2 clock signals. The counter output is thus produced at an earlier point in time than is desirable, and hence fail-safe count performance is not satisfied.
As a fault mode for the frequency dividing circuits which make up the counter, a fault wherein the output becomes fixed, or a short circuit fault between the input and output can be considered. If such a fault occurs in any one of the n frequency dividing circuits, then the counter output becomes fixed, or the frequency of the clock signal becomes constant so that the counter output frequency becomes higher than at the time of normal operation. Consequently with these types of faults, if the output frequency of the counter is monitored then they can be found.
The present invention takes into consideration the above situation, with the object of a first aspect of the invention being to provide a counting apparatus which can monitor if a counting operation is normal, after completion of the counting operation. Moreover an object of a second aspect of the invention is to provide a counting apparatus which starts a counting operation after first confirming a reset condition. Furthermore, an object of a third aspect of the invention is to provide a rotation stopped detection apparatus which uses a counting apparatus to detect, in a fail-safe manner, if a rotation body has stopped rotating.